Integrated circuits (or chips) comprise a silicon substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. A conductive interconnect system overlying the substrate electrically connects the doped regions to form electrical circuits.
A conventional interconnect system comprises a plurality of substantially vertical conductive vias or plugs interconnecting one or more substantially horizontal conductive layers (each horizontal layer referred to as an “M” or metallization layer), with a dielectric layer disposed between two vertically adjacent conductive layers. A typical interconnect system comprises 6-9 horizontal conductive layers, each further comprising a plurality of conductive lines or traces. Conductive vias in the first or lowest interconnect level connect underlying semiconductor device regions to overlying conductive layers. Upper level conductive vias interconnect two vertically adjacent conductive layers. The conductive vias and the conductive lines are formed by employing conventional techniques, including metal deposition, photolithographic masking, patterning and subtractive etching. Most integrated circuits employ tungsten conductive vias and aluminum conductive layers.
After fabrication, the integrated circuit is enclosed in a package comprising a plurality of externally-disposed pins or other conductive elements for connecting the packaged chip to electronic components in an electronic device. To connect the integrated circuit to die package pins, an uppermost conductive layer of the chip interconnect system comprises a plurality of conductive bond pads (referred to as the bond pad layer) for receiving a conductive element (e.g., a bond wire, solder bump or solder ball) that connects the integrated circuit to the package pins. In an aluminum-based interconnect system, the topmost aluminum layer is masked, patterned, and etched to define the aluminum bond pads therein.
FIG. 1 illustrates a device package 100 comprising package leads 102. An integrated circuit 104 is affixed within a die attach area 106. Bond pads 110 (in one embodiment formed from aluminum) disposed on an upper surface 112 of the integrated circuit 104 are connected to the package leads 102 by gold (or gold alloy) wires 114. Generally, the bond pads 110 vary between about 40-80 microns and 50-150 microns in length and width, respectively. Although square bond pads as illustrated are common, use of rectangular bond pads is also known in the prior art. The process of electrically connecting the bond pads 110 to the package leads 102 is referred to as wire bonding.
In another known package structure, referred to as flip-chip or bump bonding, the interconnecting bond wires are replaced with deposited solder bumps 120 formed on the bond pads 110 of the integrated circuit 104. See FIG. 2. Conventionally, an under-bump metallization layer (not shown) is formed intermediate the solder bumps 120 and the bond pads 110. Connection to a package 122 of FIG. 3 is accomplished by inverting the integrated circuit 104 and soldering the bumps 120 to receiving pads 124 on the package 122. The receiving pads 124 are in conductive communication with a corresponding package lead. In the example of FIG. 3 the package leads comprise an array of balls 126 in the form of a ball grid array. Thus integrated circuits formed with an aluminum interconnect system and aluminum bond pads 110 can be packaged using either the wire bond or bump bond process.
As integrated circuit devices and interconnect systems are reduced in size and made to carry higher frequency analog signals and higher data-rate digital signals, aluminum interconnect structures can impose unacceptable signal propagation delays within the chip. Also, as via openings continue to shrink it becomes increasingly difficult to deposit conductive material in the smaller openings.
Given these known disadvantages of aluminum interconnect structures, copper (and its alloys) is becoming the interconnect material of choice. Copper is a better conductor than aluminum (with a resistivity of 1.7 to 2.0 micro-ohm-cm compared to 2.7 to 3.1 micro-ohm-cm for aluminum), is less susceptible to electromigration (a phenomenon whereby an aluminum interconnect line thins and can eventually separate due to the electric field and thermal gradients formed by current flow through the line), and can be deposited at lower temperatures (thereby avoiding deleterious effects from high thermal budgets) and in smaller openings. The lower resistance of copper reduces signal propagation time. Moreover, recent advances in electroplating and electrodeposition make the process of depositing copper quite economical.
A dual damascene process, one preferred technique for forming a copper interconnect system, integrally forms both the conductive vertical via portion and the conductive horizontal interconnect portion of a copper metallization layer. A via is formed in a dielectric layer, followed by formation of an overlying horizontal trench. A metal deposition step simultaneously fills both the via and the trench, forming a complete metal interconnect layer comprising a substantially vertical conductive via and a substantially horizontal conductive runner. A chemical/mechanical-polishing step planarizes the dielectric surface by removing copper deposits formed on the surface during the copper deposition step.
An example of a prior art damascene structure is illustrated in the cross-sectional view of FIG. 4, comprising a dielectric layer 138 deposited or formed on a lower level interconnect structure 139. An opening formed in the dielectric layer 138 is filled with a suitable conductive material 140, such as copper, to form a conductive trench 142 and a conductive via 144 in contact with the lower level interconnect structure 139. The topmost metallization layer is used to fabricate copper bond pads as is well known in the art.
Although attempts have been made to wire bond to copper bond pads, these efforts remain an academic exercise and have not been implemented in commercial fabrication processes. Instead, the industry employs the flip-chip solder bump method for connecting copper bond pads to flip-chip package leads. However, if it is desired to use a wire bond package for an integrated circuit having a copper interconnect system, aluminum bond pads are fabricated over and in conductive communication with the copper interconnect structures. Bond wires can be bonded to the aluminum bond pads. Alternatively, a solder bump can be bonded to the aluminum bond pad for use with a flip chip package.
In the integrated circuit fabrication industry, a significant fraction of fabricated chips are shipped to a separate facility for packaging or preparing the wafers for subsequent assembly, according to the wire bonding or the flip-chip techniques described above. The facility is generally operated by a third-party contractor. Transportation of wafers from the manufacturing site to the packaging facility may take a few days to several weeks. Depending on market conditions and demand, the wafers may then be stored in inventory, typically for a few months, before packaging.
It is known that copper forms an oxide and corrodes when exposed to an ambient atmosphere. Thus during shipment and storage at the packaging facility, exposed copper pads will oxidize. The copper corrosion process is not self-limiting (i.e., the corrosion and oxidation continue indefinitely) and forms a complex array of oxides on the copper surface. The longer the exposure duration, the greater the propensity for an exposed copper pad to undergo such chemical changes. Since the copper oxide continues to grow without limit, the oxide depth is unknown and any cleaning process employed to remove the copper oxide may not remove all of the oxide.
To prevent oxide formation on the copper bond pads, prior to shipping the wafer to the packaging facility a semiconductor manufacturer forms an aluminum alloy layer (e.g., aluminum-copper, aluminum-silicon-copper) overlying the copper pad. The aluminum promotes formation of the self-passivating aluminum-oxide layer described above and substantially limits copper oxide formation. However, forming the aluminum layer adds two mask steps to the fabrication process. It is known that each mask layer can increase wafer cost and fabrication cycle time and lower the process yield. Thus semiconductor manufacturers seek to limit mask steps. If the semiconductor manufacturer elects not to form an aluminum layer over the copper bond pads, it will be necessary to form the aluminum layer prior to the bumping step for forming solder bumps. This would require cleaning of the copper oxide prior to packaging.
To summarize, according to the prior art, integrated circuits formed with an aluminum interconnect system and aluminum bond pads can be packaged using either the wire bond or bump bond process. Only minimal cleaning of the aluminum surface is required prior to packaging. For a copper interconnect system, the semiconductor fabricator can deposit an aluminum layer over the copper bond pads to limit copper oxide formation during shipping and storage prior to packaging, at the expense of two additional mask steps. With the aluminum layer in place, either wire bonding or flip chip packaging can be employed. According to another process, the fabricator ships the integrated circuits with exposed copper bond pads, necessitating a cleaning step prior to bumping and subsequent packaging. After cleaning, bump bonds are formed and the integrated circuit packaged in a bump bond package.
Beginning in FIG. 5, there is illustrated one prior art process for forming an aluminum layer and solder bumps for a copper interconnect structure, including the aforementioned copper oxide cleaning step. A copper bond pad 200 is formed within a trench or opening of a substrate 201 as shown. As described above, the substrate 201 comprises multiple alternating layers of dielectric and interconnects overlying a semiconductor substrate comprising doped regions.
A passivation stack 202 (typically a stack of dielectric material layers comprising silicon dioxide and/or silicon nitride) is formed over the bond pad 200. A photoresist layer (not shown in FIG. 5) is deposited, masked, patterned and developed to create an opening therein. An opening 204 is then formed in the passivation stack 202 according to the pattern in the photoresist layer. See FIG. 6.
Copper oxide on a surface 206 of the copper pad 200 is removed during a sputter clean process (also referred to as a back sputter process) wherein energetic argon ions (produced in a radio-frequency back sputter tool) represented by arrowheads 208 in FIG. 6, impinge upon the copper pad 200 through the opening 204.
An aluminum layer is deposited and etched according to a mask pattern (not shown), forming an aluminum pad 212 as illustrated in FIG. 7. This step represents a first one of the two required additional mask layers referred to above. At the interface between the copper pad 200 and the aluminum pad 212, intermetallic compounds can be formed as metal atoms of one material diffuse into the other material. Such intermetallic compounds may be brittle and susceptible to cracking, causing irregularities in the interface conductivity and degrading device performance. To avoid the formation of the intermetallic layer, a barrier layer (not shown in FIG. 7) is formed between the aluminum pad 212 and the copper pad 200. Exemplary materials comprising the barrier layer include: tantalum, tantalum-nitride and titanium nitride.
A passivation layer 214 (see FIG. 8) is formed and patterned, defining an opening 216 according to a patterned photoresist layer (not shown in FIG. 8). This photoresist step represents a second of the two required additional mask layers.
Hence, either the semiconductor fabrication facility or the bumping house forms aluminum pads over the copper bond pads, as described above. The wafer is delivered for solder bump formation with exposed aluminum pads. The first process performed in a bump-bonding packaging operation is cleaning of the aluminum pad 212. In this cleaning step argon ions, represented by arrowheads 217 in FIG. 8, are produced in a radio-frequency (RF) back-sputtering tool and impinge upon the aluminum pad 212 to reduce any aluminum oxide formed thereon. This oxide removal step is typically carried out in the same sputter deposition tool where the under-bump metallization (UBM) material is deposited, as described below.
Prior to formation of the UBM layer, sometimes the bumping house prefers to deposit an additional aluminum layer on the aluminum pad 212 to present a clean surface for the UBM layer. Another mask step is required to form this aluminum layer, thus increasing the cost and process cycle time.
An under-bump metallization layer 218 (see FIG. 9) is formed and patterned according to a mask layer pattern not shown in FIG. 9. Exemplary compounds for the UBM layer 218 comprise: titanium-nickel-vanadium or copper-chromium-nickel. A solder bump 220 is formed by conventional techniques overlying the under-bond metallization layer 218 as shown in FIG. 10.
In a wire bonding process, the under-bump metallization layer is not required. Instead, a wire bond is formed on the aluminum pad 212 to connect the integrated circuit to the package.
It is known that the conventional RF back-sputtering process (as described above in conjunction with the FIG. 6) for removing oxide (and other surface films) from the copper pad 200 can cause significant damage to the integrated circuit and the copper film surface. This damage results from the energy imparted to the surface by the energetic argon ions represented by the arrowheads 208 in FIG. 6. The surface of the copper bond pad 200 may be significantly roughened, making it difficult for the subsequent aluminum layer 212 to nucleate and grow adequately on the pad 200. Therefore, the device performance may be degraded when the RF back-sputtering process is used to clean the oxidized copper surface. In the worst case, wafer plasma damage can occur, rendering the device useless.